Method and apparatus for enhanced link training in a wireline communications system

ABSTRACT

Training a link between a physical layer transceiver and a link partner includes encoding, at the physical layer transceiver, a first number of training bits into a second number of encoded training bits, expanding at the physical layer transceiver the second number of encoded training bits into a third number of expanded training bits, and interpolating at the physical layer transceiver, in a first mode, between the third number of expanded training bits and a fourth number of interpolated training bits. The fourth number is more than twice the third number, and may be four times the third number. Such training may further include interpolating at the physical layer transceiver, in a second mode, between the third number of expanded training bits and the fourth number of interpolated training bits, fourth number being twice the third number. The second mode may be used when the first mode is not supported.

CROSS REFERENCE TO RELATED APPLICATION

This disclosure claims the benefit of copending, commonly-assigned U.S.Provisional Patent Application No. 63/045,706, filed Jun. 29, 2020,which is hereby incorporated by reference herein in its entirety.

FIELD OF USE

This disclosure relates to improving the accuracy of wireline dataexchanges. More particularly, this disclosure relates to improvingdecoding accuracy of data exchanges in wireline systems, such asEthernet systems, by increasing the number of bits used for training.

BACKGROUND

The background description provided herein is for the purpose ofgenerally presenting the context of the disclosure. Work of theinventors hereof, to the extent the work is described in this backgroundsection, as well as aspects of the description that may not otherwisequalify as prior art at the time of filing, are neither expressly norimpliedly admitted to be prior art against the subject matter of thepresent disclosure.

Initiation of wireline communications between physical layertransceivers, such as Ethernet communications under various versions ofthe IEEE 802.3 standard, includes a training period involving theexchange of training data. However, as data rates increase relative tothe amount of training data, the chance for transmission error alsoincreases, decreasing the likelihood of successful decoding.

SUMMARY

In a physical layer transceiver, training circuitry, in accordance withimplementations of the subject matter of this disclosure, for training alink with a link partner, includes encoder/decoder circuitry configuredto convert between a first number of training bits and a second numberof encoded training bits, expander/compressor circuitry configured toconvert between the second number of encoded training bits and a thirdnumber of expanded training bits, and interpolator/decimator circuitryconfigured to operate in a first mode to convert between the thirdnumber of expanded training bits and a fourth number of interpolatedtraining bits, wherein the fourth number is more than twice the thirdnumber.

In a first implementation of such training circuitry, in the first modeof the interpolator/decimator circuitry, the fourth number may be fourtimes the third number.

In a second implementation of such training circuitry, theinterpolator/decimator circuitry may be further configured to operate ina second mode wherein the fourth number is twice the third number.

In a third implementation of such training circuitry of, the thirdnumber may be 64, In the first mode, the fourth number may be 256, andin the second mode, the fourth number may be 128.

In a fourth implementation of such training circuitry, theencoder/decoder circuitry may implement Differential ManchesterEncoding.

In a fifth implementation of such training circuitry, the second numbermay be twice the first number.

In a sixth implementation of such training circuitry, the third numbermay be four times the second number.

In a seventh implementation of such training circuitry, the first numbermay be 8, the second number may be 16, the third number may be 64, andthe fourth number may be 256.

A method, according to implementations of the subject matter of thisdisclosure, for training a link between a physical layer transceiver anda link partner, includes encoding at the physical layer transceiver afirst number of training bits into a second number of encoded trainingbits, expanding at the physical layer transceiver the second number ofencoded training bits into a third number of expanded training bits, andinterpolating at the physical layer transceiver, in a first mode,between the third number of expanded training bits and a fourth numberof interpolated training bits, wherein the fourth number is more thantwice the third number.

In a first implementation of such a method, in the interpolating, thefourth number may be four times the third number.

A second implementation of such a method may further includeinterpolating at the physical layer transceiver, in a second mode,between the third number of expanded training bits and the fourth numberof interpolated training bits, where the fourth number is twice thethird number.

A first aspect of that second implementation, may further includedetermining, at the physical layer transceiver, whether the link partnersupports the first mode, when it is determined that the link partnersupports the first mode, performing the interpolating in the first mode,and when it is determined that the link partner does not support thefirst mode, performing the interpolating in the second mode.

In a first instance of that first aspect, the determining may beperformed during negotiation with the link partner.

In a third implementation of such a method, the third number may be 64,in the first mode, the fourth number may be 256, and in the second mode,the fourth number may be 128.

In a fourth implementation of such a method, the encoding may beperformed using Differential Manchester Encoding.

In a fifth implementation of such a method, the second number may betwice the first number.

In a sixth implementation of such a method, the third number may be fourtimes the second number.

In a seventh implementation of such a method, the first number may be 8,the second number may be 16, the third number may be 64, and the fourthnumber may be 256.

A wireline communications system according to implementations of thesubject matter of this disclosure includes a wireline communicationsmedium, a first physical layer transceiver coupled to the wirelinecommunications medium, and a second physical layer transceiver coupledto the wireline communications medium, wherein each respective one ofthe first physical layer transceiver and the second physical layertransceiver includes respective training circuitry, for training a linkwith the other respective one of the first physical layer transceiverand the second physical layer transceiver, the respective trainingcircuitry including respective encoder/decoder circuitry configured toconvert in either direction between a first number of training bits anda second number of encoded training bits, respective expander/compressorcircuitry configured to convert in either direction between the secondnumber of encoded training bits and a third number of expanded trainingbits, and respective interpolator/decimator circuitry configured tooperate in a first mode to convert in either direction between the thirdnumber of expanded training bits and a fourth number of interpolatedtraining bits, where the fourth number is more than twice the thirdnumber.

In a first implementation of such a wireline communications system, therespective interpolator/decimator circuitry may be further configured tooperate in a second mode where the fourth number is twice the thirdnumber.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features of the disclosure, its nature and various advantages,will be apparent upon consideration of the following detaileddescription, taken in conjunction with the accompanying drawings, inwhich like reference characters refer to like parts throughout, and inwhich:

FIG. 1 is a schematic representation of a wireline communications systemin accordance with implementations of the subject matter of thisdisclosure;

FIG. 2 is a representation of a training frame structure which may beused in implementations of the subject matter of this disclosure;

FIG. 3 is a diagrammatic representation of data flow in implementationsof the subject matter of this disclosure;

FIG. 4 is a flow diagram illustrating operation of implementations ofthe subject matter of this disclosure in the transmit direction; and

FIG. 5 is a flow diagram illustrating operation of implementations ofthe subject matter of this disclosure in the receive direction.

DETAILED DESCRIPTION

Link partners on a wireline communications link, such as Ethernetphysical layer transceivers on a wired or backplane Ethernet connection,typically perform a training procedure to establish a link with thelowest possible bit error rate. The link partners typically begin byexchanging a list of capabilities, including transmission rates andequalization capabilities, and agreeing on a training rate (typicallythe highest common rate among the two sets of capabilities). The twolink partners begin exchanging training data at the agreed rate, witheach partner applying equalization to the data and examining theresulting equalized data (e.g., data eye characteristics), andrequesting that the other partner retransmit at different rates and/orfilter settings until each partner is satisfied with the received data.

A wireline communications system may have the general structure shown inFIG. 1. A first physical layer transceiver (PHY) 100 couples a firsthost, such as functional module 101, to wireline channel medium (cable)102, using encoding and decoding circuitry 103. One or more adaptivefilters, shown as echo canceller(s) 106, but also potentially includingnear-end crosstalk (NEXT) canceller(s) and far-end crosstalk (FEXT)canceller(s), filter the effects of interference from echo and/ornear-end crosstalk and/or far-end crosstalk, respectively. A second PHY120 couples a second host, such as functional module 121, to wirelinechannel medium (cable) 102, using encoding and decoding circuitry 123.One or more adaptive filters, shown as echo canceller(s) 126, but alsopotentially including near-end crosstalk (NEXT) canceller(s) and far-endcrosstalk (FEXT) canceller(s), filter the effects of interference fromecho and/or near-end crosstalk and/or far-end crosstalk, respectively.

In some implementations according to the subject matter of thisdisclosure, PHY 100 transmits data through digital-to-analog converter104 from functional module 101 onto link 102 via encoder/decoder 103,and receives from link 102, via encoder/decoder 103 throughanalog-to-digital converter 105, a remote (target) signal and an echo ofthe transmitted signal, for delivery to functional module 101. Digitalecho canceler 106 may be used to remove the echo, and may also includenear-end crosstalk (NEXT) canceller(s) and far-end crosstalk (FEXT)canceller(s), to filter the effects of interference from echo and/ornear-end crosstalk and/or far-end crosstalk, respectively. Equalizer 107is used to enhance the quality of the received remote signal. The remotesignal may be from functional module 121, transmitted onto link 102 byPHY 120.

A training mode is used to establish a link between PHY 100 and PHY 120.In that training mode, training data is processed through trainingcircuitry including encoder/decoder 103 for transmission onto link 102.In an implementation of a 100 Gbps system such as 100GBASE-KR under theIEEE 802.3ck standard, used over backplanes, the training data may havethe training frame structure 200 shown in FIG. 2. Training pattern 201includes 2¹⁴=16384 unit intervals (UI), each of which is occupied by onedata value. In some implementations, the data values may be bits (i.e.,‘0’ or ‘1’), but in other implementations, the data may be encoded using4-level pulse amplitude modulation (PAM-4) where each data value can be‘0’, ‘1’, ‘2’ or ‘3’. Training pattern 201 is preceded by frame marker202, control field 203 and status field 204, which collectively may bereferred to as the Transmitter Training Information Unit (TTIU) 205.Frame marker 202 may occupy 32 UI, which in a PAM-4 implementation maybe 16 3's followed by 16 0's. Control field 203 and status field 204 mayeach occupy 128 UI.

In accordance with implementations of the subject matter of thisdisclosure, when one of PHY 100 and PHY 120 is acting in its role astransmitter, bits of TTIU 205 are processed (e.g., in training circuitryincluding encoder/decoder 103) as shown in FIG. 3, with every 8 bitstransformed into 128 bits of data for transmission onto link 102 totrain a connection with its remote link partner, which may be the otherone of PHY 100 and PHY 120, or may be another link partner. First, 8bits 300 are provided by controller 110/130 and encoded using, forexample, Differential Manchester Encoding (DME) in DME encoder/decoder301. In DME, a ‘0’ becomes either ‘00’ or ‘11’, while a ‘1’ becomeseither ‘01’ or ‘10’. Thus, the number of bits is doubled so that 8 bits300 become 16 DME-encoded bits 311.

The 16 DME-encoded bits 311 of this implementation are expanded in DMEbit-expander/compressor 302. During expansion, each ‘0’ becomes fourzeroes, while each ‘1’ becomes four ones, so that the 16 DME-encodedbits 311 become 64 bits of DME expanded data 312. The 64 bits of DMEexpanded data 312 are processed in bit interpolator/decimator 303 tointerpolate every bit three additional times (so that each bit againbecomes four identical bits), yielding, in this implementation 256 bitsof converted 100 Gbps training data 313.

The process is reversed during training when PHY 100 or PHY 120 isacting in its role as receiver (which happens alternately with its roleas transmitter during the training). 256 bits of received 100 Gbpstraining data 313 are processed in bit interpolator/decimator 303(decimating each group of four bits into one bit) to yield 64 bits ofDME expanded data 312. In this direction, DME bit-expander/compressor302 compresses the 64 bits of DME expanded data 312 to yield 16DME-encoded bits 311. The 16 DME-encoded bits 311 are decoded in DMEencoder/decoder 301 to yield 8 TTIU bits 300 for processing bycontroller 310.

However, the link partner may be a device that does not implement thesubject matter of this disclosure, but rather, for example, is a typicalimplementation under the IEEE 802.3ck standard. Such a device will nothave a bit interpolator/decimator 303 capable of converting 64 bits ofDME expanded data into 256 bits of converted 100 Gbps training data, orof converting 256 bits of 100 Gbps training data back into 64 bits ofDME expanded data. Instead, it may include a bit interpolator/decimatorcapable of converting 64 bits of DME expanded data into 128 bits ofconverted 100 Gbps training data, or of converting 128 bits of 100 Gbpstraining data back into 64 bits of DME expanded data.

Therefore, the training mode according to implementations of the subjectmatter of this disclosure, such as the implementation according to FIG.3, operates when training circuitry in both link partners includes bitinterpolator/decimator 303 and can convert 64 bits of DME expanded datainto 256 bits of converted 100 Gbps training data, and can convert 256bits of 100 Gbps training data back into 64 bits of DME expanded data,which is twice as many bits as a typical implementation under the IEEE802.3ck standard. Implementations according to the subject matter ofthis disclosure, such as the implementation according to FIG. 3, thushave twice as many data bits to work with during link training, andtherefore are expected to have a better decoding result duringhigh-speed operations, as compared to devices operating in a trainingmode implemented under the IEEE 802.3ck standard. Therefore, devicesimplemented according to the subject matter of this disclosure mayoperate successfully at rates as high as 112 Gbps or greater.

Nevertheless, for compatibility with devices implemented under the IEEE802.3ck standard, in which the bit interpolator/decimator converts 64bits of DME expanded data into 128 bits of converted 100 Gbps trainingdata, or converts 128 bits of 100 Gbps training data back into 64 bitsof DME expanded data, bit interpolator/decimator 303 in implementationsof the subject matter of this disclosure is also capable ofinteroperating with a bit interpolator/decimator in a remote linkpartner to process 128 bits of training data rather than 256 bits oftraining data. The determination to operate in the 256-bit mode or the128-bit mode may be made, for example, during the initial negotiationbetween PHY 100 and the remote link partner, when the identity of theremote link partner becomes known to PHY 100.

In the transmit direction, implementations according to the subjectmatter of this disclosure may operate in accordance with method 400,diagrammed in FIG. 4. At 401, a first number of training bits (e.g., 8training bits in the implementation shown in FIG. 3) of training dataare encoded to yield a second number of encoded bits (e.g., 16 encodedbits in the implementation shown in FIG. 3) of encoded data. At 402, theencoded bits are expanded to yield a third number (e.g., 64 bits in theimplementation shown in FIG. 3) of expanded bits.

At 403, it is determined whether the link partner is capable of enhanceddata conversion (e.g., by interpolation/decimation) in accordance withimplementations of the subject matter of this disclosure. If so, then at404, the third number of expanded bits are interpolated to a fourthnumber of bits more than twice the third number of expanded bits (e.g.,256 bits, or four times the number of expanded bits, in theimplementation shown in FIG. 3).

If at 403, it is determined that the link partner is not capable ofenhanced data conversion in accordance with implementations of thesubject matter of this disclosure, then at 405, the third number ofexpanded bits are interpolated to a fourth number of bits that is twicethe third number of expanded bits (e.g., 128 bits; cf. FIG. 3).

At 406, the interpolated data bits output at 404 or 405 are transmittedby PHY 100 to the link partner for decoding to train the link beingestablished, and method 400 ends.

Similar data may be transmitted by the link partner and received by PHY100 for decoding by PHY 100 to train the link. In the receive direction,implementations according to the subject matter of this disclosure mayoperate in accordance with method 500, diagrammed in FIG. 5.

At 501, a first number of data bits is received by PHY 100 from the linkpartner for decoding to train the link being established. At 502, it isdetermined whether the link partner is capable of enhanced dataconversion (e.g., by interpolation/decimation) in accordance withimplementations of the subject matter of this disclosure. If so, thenthe received data bits are assumed to have been interpolated at the linkpartner at a higher multiple than two-to-one, and at 503 the receiveddata bits are decimated into a second number of bits of expanded data,where the second number is less than half the first number (e.g.,one-quarter of the first number). But if at 502 it is determined thatthe link partner is not capable of enhanced data conversion inaccordance with implementations of the subject matter of thisdisclosure, then the received data bits are assumed to have beeninterpolated at the link partner at a multiple of two-to-one, and at 504the received data bits are decimated into a second number of bits ofexpanded data, where the second number is half the first number.

At 505, the expanded data bits output at 503 or 504 are compressed toyield a third number of bits of encoded data. At 506, the third numberof bits of encoded data are decoded to yield a fourth number of bits ofdecoded data, and method 500 ends. The decoded output bits are used bycontroller 110/130 in training the link.

Thus it is seen that interpolated training data with more databits—e.g., twice as many data bits—to work with during link training, sothat training can be expected to have a better decoding result duringhigh-speed operations, has been provided.

As used herein and in the claims which follow, the construction “one ofA and B” shall mean “A or B.”

It is noted that the foregoing is only illustrative of the principles ofthe invention, and that the invention can be practiced by other than thedescribed embodiments, which are presented for purposes of illustrationand not of limitation, and the present invention is limited only by theclaims which follow.

What is claimed is:
 1. Training circuitry in a physical layer transceiver, for training a link with a link partner, the training circuitry comprising: encoder/decoder circuitry configured to convert between a first number of training bits and a second number of encoded training bits; expander/compressor circuitry configured to convert between the second number of encoded training bits and a third number of expanded training bits; and interpolator/decimator circuitry configured to operate in a first mode to convert between the third number of expanded training bits and a fourth number of interpolated training bits by, when interpolating, repeating each bit in the expanded training bits by a repetition factor equal to the fourth number and, when decimating, reducing each group of the fourth number of bits to one bit, wherein the fourth number is more than twice the third number.
 2. The training circuitry of claim 1, wherein in the first mode of the interpolator/decimator circuitry, the fourth number is four times the third number.
 3. The training circuitry of claim 1, wherein the interpolator/decimator circuitry is further configured to operate in a second mode wherein the fourth number is twice the third number.
 4. The training circuitry of claim 3, wherein: the third number is 64; in the first mode, the fourth number is 256; and in the second mode, the fourth number is
 128. 5. The training circuitry of claim 1, wherein the encoder/decoder circuitry implements Differential Manchester Encoding.
 6. The training circuitry of claim 1, wherein the second number is twice the first number.
 7. The training circuitry of claim 1, wherein the third number is four times the second number.
 8. The training circuitry of claim 1, wherein: the first number is 8; the second number is 16; the third number is 64; and the fourth number is
 256. 9. A method of training a link between a physical layer transceiver and a link partner, the method comprising: encoding at the physical layer transceiver a first number of training bits into a second number of encoded training bits; expanding at the physical layer transceiver the second number of encoded training bits into a third number of expanded training bits; and interpolating at the physical layer transceiver, in a first mode, between the third number of expanded training bits and a fourth number of interpolated training bits by repeating each bit in the expanded training bits by a repetition factor equal to the fourth number, wherein the fourth number is more than twice the third number.
 10. The method of claim 9, wherein in the interpolating, the fourth number is four times the third number.
 11. The method of claim 9, further comprising interpolating at the physical layer transceiver, in a second mode, between the third number of expanded training bits and the fourth number of interpolated training bits, wherein the fourth number is twice the third number.
 12. The method of claim 11, further comprising: determining, at the physical layer transceiver, whether the link partner supports the first mode; when it is determined that the link partner supports the first mode, performing the interpolating in the first mode; and when it is determined that the link partner does not support the first mode, performing the interpolating in the second mode.
 13. The method of claim 12 wherein the determining is performed during negotiation with the link partner.
 14. The method of claim 11, wherein: the third number is 64; in the first mode, the fourth number is 256; and in the second mode, the fourth number is
 128. 15. The method of claim 9, wherein the encoding is performed using Differential Manchester Encoding.
 16. The method of claim 9, wherein the second number is twice the first number.
 17. The method of claim 9, wherein the third number is four times the second number.
 18. The method of claim 9, wherein: the first number is 8; the second number is 16; the third number is 64; and the fourth number is
 256. 19. A wireline communications system comprising: a wireline communications medium; a first physical layer transceiver coupled to the wireline communications medium; and a second physical layer transceiver coupled to the wireline communications medium; wherein: each respective one of the first physical layer transceiver and the second physical layer transceiver includes respective training circuitry, for training a link with the other respective one of the first physical layer transceiver and the second physical layer transceiver, the respective training circuitry comprising: respective encoder/decoder circuitry configured to convert in either direction between a first number of training bits and a second number of encoded training bits; respective expander/compressor circuitry configured to convert in either direction between the second number of encoded training bits and a third number of expanded training bits; and respective interpolator/decimator circuitry configured to operate in a first mode to convert in either direction between the third number of expanded training bits and a fourth number of interpolated training bits by, when interpolating, repeating each bit in the expanded training bits by a repetition factor equal to the fourth number and, when decimating, reducing each group of the fourth number of bits to one bit, wherein the fourth number is more than twice the third number.
 20. The wireline communications system of claim 19 wherein the respective interpolator/decimator circuitry is further configured to operate in a second mode wherein the fourth number is twice the third number. 